The present disclosure generally relates to storage systems comprising solid state memory devices such as flash based memory devices, and to techniques for controlling such solid state memory devices, in particular with a focus on decoding mechanisms for such solid state memory devices.
Solid-state memory devices encompass rewritable non-volatile memory devices which use electronic circuitry for storing data. Currently, solid-state memory devices start replacing conventional storage devices such as hard disk drives and optical disk drives in some arenas, such as in mass storage applications for laptops or desktops. Solid state memory devices are also investigated for replacing conventional storage devices in other areas such as in enterprise storage systems. This is because solid state memory devices offer exceptional bandwidth as well as excellent random I/O (input/output) performance along with an appreciated robustness due to lack of moveable parts.
State-of-the-art solid-state drives (SSD)—which term is used equivalently to the term solid state memory device—may be embodied with single-level cells (SLC) for which binary quantization is performed to yield one bit of information, or with multi-level cells (MLC) for which quantization to one of several levels, usually four or eight, is performed to yield more than one bit of information.
Error-correction codes (ECC) may be applied to solid state drives to achieve the required reliability of the data retrieval process. Typically, Reed-Solomon (RS) or Bose-Chaudhuri-Hocquenghem (BCH) codes are used for that purpose, in conjunction with hard decoding algorithms. The main problem with hard decoding algorithms is that non-recoverable loss of information occurs whenever a quantization is performed on the physical value that is read back from a memory cell. To overcome the loss of information caused by hard decoding techniques, soft decoding of ECC has been recently proposed for SSDs. Soft decoding techniques are characterized by decoding a codeword within multiple iterations. It is known that soft decoding yields large coding gains compared to RS codes. However, iterative decoding introduces a latency associated with the decoding process, which may adversely affect the response time of SSD applications.
An iterative decoding technique is applied to a solid state memory device in WO 2007/084751 A2 in which the device includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
Another iterative decoder is illustrated in US 2009/0024905 A1 in which the corresponding method for operating a memory device includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analogue values in respective analogue memory cells of the memory device. After storing the encoded data, second analogue values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analogue values differ from the respective first analogue values. A distortion that is present in the second analogue values is estimated. Error correction metrics are computed with respect to the second analogue values responsively to the estimated distortion. The second analogue values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.